1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming semiconductor devices while preventing or reducing loss of active area and/or isolation regions.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a planar device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region and separated therefrom by a gate insulation layer. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If there is no voltage applied to the gate electrode, then there is no current flow through the device (ignoring undesirable leakage currents, which are relatively small). However, when an appropriate voltage is applied to the gate electrode, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and to prevent the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a FET, which has a planar structure, a so-called FinFET device has a three-dimensional (3D) structure. More specifically, in a FinFET, a generally vertically positioned fin-shaped active area is formed and a gate electrode encloses both sides and an upper surface of the fin-shaped active area to form a tri-gate structure so as to use a channel having a three-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fin and the FinFET device only has a dual-gate structure. Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to reduce at least some short channel effects.
For many early device technology generations, the gate structures of most transistor devices, whether a planar device or a 3D device, have been comprised of a plurality of silicon-based materials, such as a silicon dioxide and/or silicon oxynitride gate insulation layer, in combination with a polysilicon gate electrode. However, as the channel length of aggressively scaled transistor elements has become increasingly smaller, many newer generation devices employ gate structures that contain alternative materials in an effort to avoid the short channel effects which may be associated with the use of traditional silicon-based materials in reduced channel length transistors. For example, in some aggressively scaled transistor elements, which may have channel lengths on the order of approximately 10-20 nm or less, gate structures that include a so-called high-k dielectric gate insulation layer and one or more metal layers that function as the gate electrode (HK/MG) have been implemented. Such alternative gate structures have been shown to provide significantly enhanced operational characteristics over the heretofore more traditional silicon dioxide/polysilicon gate structure configurations.
Depending on the specific overall device requirements, several different high-k materials—i.e., materials having a dielectric constant, or k-value, of approximately 10 or greater—have been used with varying degrees of success for the gate insulation layer in an HK/MG gate electrode structure. For example, in some transistor element designs, a high-k gate insulation layer may include tantalum oxide (Ta2O5), hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), aluminum oxide (Al2O3), hafnium silicates (HfSiOx) and the like. Furthermore, one or more non-polysilicon metal gate electrode materials—i.e., a metal gate stack—may be used in HK/MG configurations so as to control the work function of the transistor. These metal gate electrode materials may include, for example, one or more layers of titanium (Ti), titanium nitride (TiN), titanium-aluminum (TiAl), aluminum (Al), aluminum nitride (AlN), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), tantalum silicide (TaSi) and the like.
There are two well-known processing methods for forming a planar or 3D transistor with a high-k/metal gate structure: (1) the so-called “gate last” or “replacement gate” technique; and (2) the so-called “gate first” technique. In the replacement gate technique, a so-called “dummy” or sacrificial gate structure is initially formed and remains in place as many process operations are performed to form the device, e.g., the formation of doped source/drain regions, performing an anneal process to repair damage to the substrate caused by the ion implantation processes and to activate the implanted dopant materials. At some point in the process flow, the sacrificial gate structure is removed to define a gate cavity where the final HK/MG gate structure for the device is formed. In general, using the “gate first” technique involves forming a stack of layers of material across the substrate, wherein the stack of materials includes a high-k gate insulation layer, one or more metal layers, a layer of polysilicon and a protective cap layer, e.g., silicon nitride. Thereafter, one or more etching processes are performed to pattern the stack of materials to thereby define the basic gate structures for the transistor devices.
FIGS. 1A-1D depict one illustrative prior art “gate first” technique that will be discussed in connection with some problems that may arise when using the gate first technique. As shown in FIG. 1A, the integrated circuit product 10 includes an illustrative PFET device 10P and an NFET device 10N that are formed in active regions of a semiconducting substrate 12. An illustrative trench isolation region 14 electrically isolates the devices 10P, 10N from one another. At the point of fabrication depicted in FIG. 1A, the gate structures 16P, 16N have been formed for the PFET device 10P and NFET device 10N, respectively. In the depicted example, the isolation region 14 has an uneven or gouged upper surface due to the undesirable consumption of some of the isolation regions 14 during previous processing operations. The gate structures 16P, 16N are generally comprised of a high-k gate insulation layer 18, one or more metal layers 20P, 20N, a layer of polysilicon 22 and gate cap layers 24P, 24N. Also depicted in FIG. 1A are illustrative sidewall spacers 26, e.g., silicon nitride. The number of metal layers and the types of metal layers employed in the PFET device 10P and NFET device 10N may be different. In general, the gate cap layer 24N on the NFET device 10N tends to be thicker than the gate cap layer 24P on the PFET device 10P. This situation typically occurs because an additional hard mask layer is formed on the NFET device 10N when silicon/germanium material (not shown) is grown in cavities (not shown) that were formed in the substrate 12 adjacent the gate structure 16P for the PFET device 10P.
The protective cap layers 24P, 24N and the spacers 26 were formed to protect the gate structures 16P, 16N from subsequent processing operations after the gates were patterned. At the point of processing depicted in FIG. 1A, the protective cap layers 24P, 24N must be removed so that a metal silicide region may be formed in the polysilicon gate material 22 so as to thereby reduce its contact resistance. But, it is also desirable that the spacers 26 remain in place so as to protect the gate structures 16P, 16N. Unfortunately, the spacers 26 and the gate cap layers 24P, 24N are typically made of the same material, e.g., silicon nitride, due to the effectiveness of that material in terms of being able to withstand many common processing operations and thereby provide good protection to the gate structures 16P, 16N. Thus, it is desirable that the gate cap layers 24P, 24N be removed while leaving in place the sidewall spacers 26.
As shown in FIG. 1B, a relatively thin layer of silicon dioxide 28 is deposited across the product 10. The purpose of the layer 28 is to protect the sidewall spacer 26 when the gate cap layers 24P, 24N are removed.
FIG. 1C depicts the device 10 after a dry, anisotropic etching process has been performed to remove all of the horizontally positioned portions of the layer of silicon dioxide 28. This results in the formation of spacer-type layers of silicon dioxide 28A on the sidewall spacer 26. This etching process operation exposes the upper surface 25 of the cap layers 24P, 24N so that they may subsequently be removed. Unfortunately, the etching process that is used to remove portions of the layer of silicon dioxide 28 also etches undesirable recesses 30 in the active regions of the substrate 12 and consumes additional portions of the isolation region 14. The depth of the recesses 30 may vary depending upon the particular application, e.g., the recesses may have a depth that falls within the range of about 7-21 nm. Loss of material in the active region can result in performance loss for the device, e.g., the extension implants for the device may be located deeper in the substrate due to the loss of active region material, which may lead to different electrical behavior for the device. FIG. 1D depicts the device 10 after an etching process was performed to remove the gate cap layers 24P, 24N. The etching process also recesses the spacers 26 to a limited degree.
The present disclosure is directed to various methods of forming semiconductor devices while preventing or reducing loss of active area and/or isolation regions that may avoid, or at least reduce, the effects of one or more of the problems identified above.